GS816032BT-200 Datasheet, GSI Technology

* FT pin for user-configurable flow through or pipeline operation
* Single Cycle Deselect (SCD) operation
* 2.5 V or 3.3 V +10%/
  –10% core powe.

* JEDEC-standard 100-lead TQFP package
* RoHS-compliant 100-lead TQFP package available 1M x 18, 512K x 32, 512.

Applications The GS816018/32/36BT is an 18,874,368-bit (16,777,216-bit for x32 version) high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high perfo.